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| 0 R XC9500 In-System Programmable CPLD Family 0 1* September 15, 1999 (Version 5.0) Features * High-performance - 5 ns pin-to-pin logic delays on all pins - fCNT to 125 MHz Large density range - 36 to 288 macrocells with 800 to 6,400 usable gates 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of multiple XC9500 devices Family Overview The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint. The XC9500 architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. An expanded JTAG instruction set allows version control of programming patterns and in-system debugging. In-system programming throughout the full device operating range and a minimum of 10,000 program/erase cycles provide worry-free reconfigurations and system field upgrades. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. I/Os may be configured for 3.3 V or 5 V operation. All outputs provide 24 mA drive. * * * * * * * * * * * * * Architecture Description Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with 36 inputs and 18 outputs. The FastCONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs. See Figure 1. September 15, 1999 (Version 5.0) 1 R XC9500 In-System Programmable CPLD Family 3 JTAG Port JTAG Controller In-System Programming Controller 36 I/O I/O I/O I/O 18 Function Block 1 Macrocells 1 to 18 FastCONNECT Switch Matrix 36 18 Function Block 2 Macrocells 1 to 18 I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2 or 4 36 18 Function Block 3 Macrocells 1 to 18 36 18 Function Block N Macrocells 1 to 18 X5877 Figure 1: XC9500 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. Table 1: XC9500 Device Family XC9536 Macrocells Usable Gates Registers tPD (ns) tSU (ns) tCO (ns) fCNT (MHz) fSYSTEM (MHz) 36 800 36 5 3.5 4.0 100 100 XC9572 72 1,600 72 7.5 4.5 4.5 125 83.3 XC95108 108 2,400 108 7.5 4.5 4.5 125 83.3 XC95144 144 3,200 144 7.5 4.5 4.5 125 83.3 XC95216 216 4,800 216 10 6.0 6.0 111.1 66.7 XC95288 288 6,400 288 10 6.0 6.0 111.1 66.7 Note: fCNT = Operating frequency for 16-bit counters fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs. 2 September 15, 1999 (Version 5.0) R XC9500 In-System Programmable CPLD Family Table 2: Available Packages and Device I/O Pins (not including dedicated JTAG pins) XC9536 44-Pin VQFP 44-Pin PLCC 48-Pin CSP 84-Pin PLCC 100-Pin TQFP 100-Pin PQFP 160-Pin PQFP 208-Pin HQFP 352-Pin BGA 34 34 34 XC9572 34 69 72 72 69 81 81 108 XC95108 XC95144 XC95216 XC95288 81 81 133 133 166 166 168 192 Function Block Each Function Block, as shown in Figure 2, is comprised of 18 independent macrocells, each capable of implementing a combinatorial or registered function. The FB also receives global clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the FastCONNECT switch matrix. These 18 outputs and their corresponding output enable signals also drive the IOB. Logic within the FB is implemented using a sum-of-products representation. Thirty-six inputs provide 72 true and complement signals into the programmable AND-array to form 90 product terms. Any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator. Each FB (except for the XC9536) supports local feedback paths that allow any number of FB outputs to drive into its own programmable AND-array without going outside the FB. These paths are used for creating very fast counters and state machines where all state registers are within the same FB. 5 Macrocell 1 Programmable AND-Array From FastCONNECT Switch Matrix Product Term Allocators 18 36 18 18 OUT PTOE To FastCONNECT Switch Matrix To I/O Blocks Macrocell 18 1 Global Set/Reset 3 Global Clocks X5878 Figure 2: XC9500 Function Block September 15, 1999 (Version 5.0) 3 R XC9500 In-System Programmable CPLD Family Macrocell Each XC9500 macrocell may be individually configured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Figure 3. Five direct product terms from the AND-array are available for use as primary data inputs (to the OR and XOR gates) to implement combinatorial functions, or as control inputs including clock, set/reset, and output enable. The product term allocator associated with each macrocell selects how the five direct terms are used. The macrocell register can be configured as a D-type or T-type flip-flop, or it may be bypassed for combinatorial operation. Each register supports both asynchronous set and reset operations. During power-up, all user registers are initialized to the user-defined preload state (default to 0 if unspecified). 36 Global Set/Reset Global Clocks 3 Additional Product Terms (from other macrocells) Product Term Set 1 0 S D/T Q Product Term Allocator To FastCONNECT Switch Matrix Product Term Clock Product Term Reset R OUT Product Term OE PTOE To I/O Blocks Additional Product Terms (from other macrocells) X5879 Figure 3: XC9500 Marcocell Within Function Block 4 September 15, 1999 (Version 5.0) R XC9500 In-System Programmable CPLD Family All global control signals are available to each individual macrocell, including clock, set/reset, and output enable signals. As shown in Figure 4, the macrocell register clock originates from either of three global clocks or a product term clock. Both true and complement polarities of a GCK pin can be used within the device. A GSR input is also provided to allow user registers to be set to a user-defined state. Macrocell Product Term Set Product Term Clock S D/T R Product Term Reset I/O/GSR Global Set/Reset I/O/GCK1 Global Clock 1 5 I/O/GCK2 Global Clock 2 I/O/GCK3 Global Clock 3 X5880 Figure 4: Macrocell Clock and Set/Reset Capability September 15, 1999 (Version 5.0) 5 R XC9500 In-System Programmable CPLD Family Product Term Allocator The product term allocator controls how the five direct product terms are assigned to each macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5. Product Term Allocator Note that the incremental delay affects only the product terms in other macrocells. The timing of the direct product terms is not changed. Product Term Allocator Macrocell Product Term Logic Product Term Allocator X5894 Figure 5: Macrocell Logic Using Direct Product Term The product term allocator can re-assign other product terms within the FB to increase the logic capacity of a macrocell beyond five direct terms. Any macrocell requiring additional product terms can access uncommitted product terms in other macrocells within the FB. Up to 15 product terms can be available to a single macrocell with only a small incremental delay of tPTA, as shown in Figure 6. Product Term Allocator Macrocell Logic With 15 P-Terms X5895 Figure 6: Product Term Allocation With 15 Product Terms 6 September 15, 1999 (Version 5.0) R XC9500 In-System Programmable CPLD Family The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in Figure 7. Product Term Allocator In this example, the incremental delay is only 2*tPTA. All 90 product terms are available to any macrocell, with a maximum incremental delay of 8*tPTA. Macrocell Logic With 2 Product Terms Product Term Allocator 5 Product Term Allocator Macrocell Logic With 18 Product Terms Product Term Allocator X5896 Figure 7: Product Term Allocation Over Several Macrocells September 15, 1999 (Version 5.0) 7 R XC9500 In-System Programmable CPLD Family The internal logic of the product term allocator is shown in Figure 8. From Upper Macrocell To Upper Macrocell Product Term Allocator Product Term Set Global Set/Reset 1 0 S D/T Q Global Clocks Product Term Clock R Product Term Reset Global Set/Reset Product Term OE From Lower Macrocell To Lower Macrocell X5881 Figure 8: Product Term Allocator Logic 8 September 15, 1999 (Version 5.0) R XC9500 In-System Programmable CPLD Family FastCONNECT Switch Matrix The FastCONNECT switch matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corresponding to user pin inputs) and all FB outputs drive the FastCONNECT matrix. Any of these (up to a FB fan-in limit of 36) may be selected, through user programming, to drive each FB with a uniform delay. The FastCONNECT switch matrix is capable of combining multiple internal connections into a single wired-AND output before driving the destination FB. This provides additional logic capability and increases the effective logic fan-in of the destination FB without any additional timing delay. This capability is available for internal connections originating from FB outputs only. It is automatically invoked by the development software where applicable. FastCONNECT Switch Matrix Function Block 5 I/O Block (36) D/T Q 18 I/O Function Block I/O Block (36) D/T Q I/O 18 Wired-AND Capability 99021101 Figure 9: FastCONNECT Switch Matrix September 15, 1999 (Version 5.0) 9 R XC9500 In-System Programmable CPLD Family I/O Block The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins. Each IOB includes an input buffer, output driver, output enable selection multiplexer, and user programmable ground control. See Figure 10 for details. The input buffer is compatible with standard 5 V CMOS, 5 V TTL and 3.3 V signal levels. The input buffer uses the internal 5 V voltage supply (VCCINT) to ensure that the input thresholds are constant and do not vary with the VCCIO voltage. The output enable may be generated from one of four options: a product term signal from the macrocell, any of the global OE signals, always "1", or always "0". There are two global output enables for devices with up to 144 macrocells, and four global output enables for devices with 180 or more macrocells. Both polarities of any of the global 3-state control (GTS) pins may be used within the device. To other Macrocells I/O Block VCCINT VCCIO To FastCONNECT Switch Matrix Macrocell Pull-up Resistor * OUT I/O (Inversion in AND-array) Product Term OE PTOE 1 UserProgrammable Ground 0 Slew Rate Control I/O/GTS1 Global OE 1 * Pull-up resistors are used to prevent floating pins during programming and other times. They are disabled during normal operations. I/O/GTS2 Global OE 2 I/O/GTS3 Global OE 3 Available in XC95216 and XC95288 I/O/GTS4 Global OE 4 X5899_01 Figure 10: I/O Block and Output Enable Capability 10 September 15, 1999 (Version 5.0) R XC9500 In-System Programmable CPLD Family Each output has independent slew rate control. Output edge rates may be slowed down to reduce system noise (with an additional time delay of tSLEW) through programming. See Figure 11. Each IOB provides user programmable ground pin capability. This allows device I/O pins to be configured as additional ground pins. By tying strategically located programmable ground pins to the external ground connection, system noise generated from large numbers of simultaneous switching outputs may be reduced. A control pull-up resistor (typically 10K ohms) is attached to each device I/O pin to prevent them from floating when the device is not in normal user operation. This resistor is active during device programming mode and system power-up. It is also activated for an erased device. The resistor is deactivated during normal operation. The output driver is capable of supplying 24 mA output drive. All output drivers in the device may be configured for either 5 V TTL levels or 3.3 V levels by connecting the device output voltage supply (VCCIO) to a 5 V or 3.3 V voltage supply. Figure 12 shows how the XC9500 device can be used in 5 V only and mixed 3.3 V/5 V systems. Pin-Locking Capability The capability to lock the user defined pin assignments during design changes depends on the ability of the architecture to adapt to unexpected changes. The XC9500 devices have architectural features that enhance the ability to accept design changes while maintaining the same pinout. The XC9500 architecture provides maximum routing within the FastCONNECT switch matrix, and incorporates a flexible Function Block that allows block-wide allocation of available product terms. This provides a high level of confidence of maintaining both input and output pin assignments for unexpected design changes. For extensive design changes requiring higher logic capacity than is available in the initially chosen device, the new design may be able to fit into a larger pin-compatible device using the same pin assignments. The same board may be used with a higher density device without the expense of board rework. 5 Output Voltage Output Voltage Standard Slew-Rated Limited tSLEW 1.5 V Standard Slew-Rated Limited tSLEW 1.5 V 0 Time 0 Time (a) (b) X5900 Figure 11: 5 V CMOS 5V 0V 5 V TTL or Output Slew-Rate For (a) Rising and (b) Falling Outputs 5V 5 V CMOS 5V VCCINT VCCIO 5 V TTL IN XC9500 CPLD ~4V OUT 0V 3.3 V GND 0V or 3.3 V 0V GND 5 V TTL 0V or IN XC9500 CPLD OUT 0V VCCINT VCCIO 3.3 V 3.3 V 5V 3.3 V 3.6 V 0V 3.3 V or 3.3 V 0V 3.6 V (a) (b) X5901 Figure 12: XC9500 Devices in (a) 5 V Systems and (b) Mixed 3.3 V/5 V Systems September 15, 1999 (Version 5.0) 11 R XC9500 In-System Programmable CPLD Family In-System Programming XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol, as shown in Figure 13. In-system programming offers quick and efficient design iterations and eliminates package handling. The Xilinx development system provides the programming data sequence using a Xilinx download cable, a third-party JTAG development system, JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. All I/Os are 3-stated and pulled high by the IOB resistors during in-system programming. If a particular signal must remain low during this time, then a pulldown resistor may be added to the pin. The TMS and TCK pins have dedicated pull-up resistors as specified by the IEEE 1149.1 standard. Boundary Scan Description Language (BSDL) files for the XC9500 are included in the development system and are available on the Xilinx FTP site. Design Security XC9500 devices incorporate advanced data security features which fully protect the programming data against unauthorized reading or inadvertent device erasure/reprogramming. Table 3 shows the four different security settings available. The read security bits can be set by the user to prevent the internal programming pattern from being read or copied. When set, they also inhibit further program operations but allow device erase. Erasing the entire device is the only way to reset the read security bit. The write security bits provide added protection against accidental device erasure or reprogramming when the JTAG pins are subject to noise, such as during system power-up. Once set, the write-protection may be deactivated when the device needs to be reprogrammed with a valid pattern. Table 3: Data Security Options Read Security Default Read Allowed Set Read Inhibited Program Inhibited/Erase Allowed Read Inhibited Program/Erase Inhibited X5905 External Programming XC9500 devices can also be programmed by the Xilinx HW130 device programmer as well as third-party programmers. This provides the added flexibility of using pre-programmed devices during manufacturing, with an in-system programmable option for future enhancements. Endurance All XC9500 CPLDs provide a minimum endurance level of 10,000 in-system program/erase cycles. Each device meets all functional, performance, and data retention specifications within this endurance limit. Write Security IEEE 1149.1 Boundary-Scan (JTAG) XC9500 devices fully support IEEE 1149.1 boundary-scan (JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS, USERCODE, INTEST, IDCODE, and HIGHZ instructions are supported in each device. For ISP operations, five additional instructions are added; the ISPEN, FERASE, FPGM, FVFY, and ISPEX instructions are fully compliant extensions of the 1149.1 instruction set. Default Program/Erase Allowed Read Allowed Set Program/Erase Inhibited 12 September 15, 1999 (Version 5.0) R XC9500 In-System Programmable CPLD Family V CC GND (a) (b) X5902 Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable 5 Low Power Mode All XC9500 devices offer a low-power mode for individual macrocells or across all macrocells. This feature allows the device power to be significantly reduced. Each individual macrocell may be programmed in low-power mode by the user. Performance-critical parts of the application can remain in standard power mode, while other parts of the application may be programmed for low-power operation to reduce the overall power dissipation. Macrocells programmed for low-power mode incur additional delay (tLP) in pin-to-pin combinatorial delay as well as register setup time. Product term clock to output and product term output enable delays are unaffected by the macrocell power-setting. Timing Model The uniformity of the XC9500 architecture allows a simplified timing model for the entire device. The basic timing model, shown in Figure 14, is valid for macrocell functions that use the direct product terms only, with standard power setting, and standard slew rate setting. Table 4 shows how each of the key timing parameters is affected by the product term allocator (if needed), low-power setting, and slew-limited setting. The product term allocation time depends on the logic span of the macrocell function, which is defined as one less than the maximum number of allocators in the product term path. If only direct product terms are used, then the logic span is 0. The example in Figure 6 shows that up to 15 product terms are available with a span of 1. In the case of Figure 7, the 18 product term function has a span of 2. Detailed timing information may be derived from the full timing model shown in Figure 15. The values and explanations for each parameter are given in the individual device data sheets. September 15, 1999 (Version 5.0) 13 R XC9500 In-System Programmable CPLD Family tSU Combinatorial Logic Combinatorial Logic D/T Q tCO Propagation Delay = tPD (a) tPSU Combinatorial Logic P-Term Clock Path tPCO Setup Time = tPSU Clock to Out Time = tPCO Internal System Cycle Time = tSYSTEM (d) D/T Q Combinatorial Logic Setup Time = tSU (b) Clock to Out Time = tCO D/T Q (c) All resources within FB using local Feedback Combinatorial Logic Combinatorial Logic D/T Q Combinatorial Logic Internal Cycle Time = tCNT (e) Setup Time Combinatorial Logic Propagation Delay = tPD + tFBK With Feedback (f) Figure 14: Basic Timing Model Pin Feedback tF tLF tLOGILP tIN tLOGI tPTCK tGCK tPTSR tGSR tPTTS tGTS S*tPTA tPDI tSLEW D/T Q tOUT tSUI tCOI tHI > tAOI tRAI tEN SR Figure 15: Detailed Timing Model Power-Up Characteristics The XC9500 devices are well behaved under all operating conditions. During power-up each XC9500 device employs internal circuitry which keeps the device in the quiescent state until the VCCINT supply voltage is at a safe level (approximately 3.8 V). During this time, all device pins and JTAG pins are disabled and all device outputs are disabled with the IOB pull-up resistors (~ 10K ohms) enabled, as shown in Table 5. When the supply voltage reaches a safe level, all user registers become initialized (typically within 100 s for 9536 - 95144, 200 s for 95216 and 300 s for 95288), and the device is immediately available for operation, as shown in Figure 16. 14 September 15, 1999 (Version 5.0) R XC9500 In-System Programmable CPLD Family If the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with the IOB pull-up resistors enabled. The JTAG pins are enabled to allow the device to be programmed at any time. If the device is programmed, the device inputs and outputs take on their configured states for normal operation. The JTAG pins are enabled to allow device erasure or boundary-scan tests at any time. FastFLASH Technology An advanced CMOS Flash process is used to fabricate all XC9500 devices. Specifically developed for Xilinx in-system programmable CPLDs, the FastFLASH process provides high performance logic capability, fast programming times, and endurance of 10,000 program/erase cycles. VCCINT Development System Support The XC9500 CPLD family is fully supported by the development systems available from Xilinx and the Xilinx Alliance Program vendors. The designer can create the design using ABEL, schematics, equations, VHDL, or Verilog in a variety of software front-end tools. The development system can be used to implement the design and generate a JEDEC bitmap which can be used to program the XC9500 device. Each development system includes JTAG download software that can be used to program the devices via the standard JTAG interface and a download cable. Table 4: Timing Model Parameters Description Propagation Delay Global Clock Setup Time Global Clock-to-output Product Term Clock Setup Time Product Term Clock-to-output Internal System Cycle Period Parameter tPD tSU tCO tPSU tPCO tSYSTEM Product Term Allocator1 + tPTA * S + tPTA * S - + tPTA * S - + tPTA * S Macrocell Low-Power Setting + tLP + tLP - + tLP - + tLP Output Slew-Limited Setting + tSLEW - + tSLEW - + tSLEW - 3.8 V (Typ) 0V No Power Quiescent State User Operation Quiescent State No Power X5904 Initialization of User Registers Figure 16: Device Behavior During Power-up 5 Note: 1. S = the logic span of the function, as defined in the text. Table 5: XC9500 Device Characteristics Device Circuitry IOB Pull-up Resistors Device Outputs Device Inputs and Clocks Function Block JTAG Controller Quiescent State Enabled Disabled Disabled Disabled Disabled Erased Device Operation Enabled Disabled Disabled Disabled Enabled Valid User Operation Disabled As Configured As Configured As Configured Enabled September 15, 1999 (Version 5.0) 15 R XC9500 In-System Programmable CPLD Family Revision History Version 3.0 4.0 5.0 Date 12/14/98 2/10/99 9/15/99 Revision Revised datasheet to reflect new AC characteristics and Internal Timing Parmeters. Corrected Figure 3 Added -10 speed grade to 95288 16 September 15, 1999 (Version 5.0) |
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